The present invention is related to the fields of electronics and Microelectromechanical Systems (MEMS). In particular, the present invention is related to electrical packaging of integrated circuits, circuit boards, electrode arrays, or other devices with compliant interconnects.
In ultra low k-ILD (interlayer dielectric) technology, the stress on the ILD layers should be minimized. Compliant interconnects with the modulated compliance to minimize the effects of mechanical and thermal stress on the ultra low-k ILD layers while still providing sufficient load bearing capability are desired.